The present invention relates generally to RF circuit switching architectures and, more particularly, to non-blocking, Nxc3x97M switching matrices.
A conventional approach to realizing a non-blocking Nxc3x97M switching matrix in RF frequency applications is shown in FIG. 1. As seen in FIG. 1, each of power dividers D1, D2, D3, and D4 are configured to receive a corresponding RF signal input at input ports designated RFin1, RFin2, RFinN-1, and RFinN, respectively. At each power divider, the RF input signal is directed to output paths 1-M. These paths are then switched in and out using 1xc3x97N switches, indicated generally at S1, S2, S3, and SN, disposed at the outputs, indicated generally at RFout1, RFout2, RFoutN-1, and RFoutN.
A principal disadvantage of the arrangement shown in FIG. 1 is that the power dividers are frequency limited. Additionally, routing every RF input signal over plural paths to reach the corresponding switch simultaneously establishes multiple leakage paths for each input. This opportunity for isolation degradation is, consequently, multiplied by the number of splits on each input. Moreover, as a consequence of this multiple stage architecture, the input paths must be routed in a fashion which creates numerous cross over points, only some of these being identified by reference numeral CO in FIG. 1. The inability to provide adequate isolation between the input signal lines has made the above-described approach wholly impractical and unsuited to implementation as a discrete IC. While it might be possible to construct a multiple layer printed circuit board (PCB) with shielded ground planes between layers to minimize cross talk and achieve acceptable isolation between signal paths, given the complexity of routing the paths in such a device, it is presently not possible to simulate or predict what level of isolation will be achieved until such a device were actually constructed and tested. In any event, it is believed that adapting the above-described matrix architecture to the ever-increasing numbers of inputs and outputs demanded by modem applications would pose substantial reliability concerns.
The aforementioned deficiencies are addressed, and an advance is made in the art, by a switching architecture having the advantages of broad bandwidth, high isolation, and an ability to be implemented at the IC level due to a systematic approach taken to ensure isolation.
The scalable Nxc3x97M switching matrix architecture of the present invention is characterized by a readily calculable number of cross over locations so that leakage can be accurately modeled and predicted. A scalable Nxc3x97M switching matrix architecture is characterized by a readily calculable number of crossover locations and comprises one or more single pole, N throw (xe2x80x9cSPNTxe2x80x9d) switches and, for each such switch, an N state impedance converter/amplitude compensation network. In accordance with the present invention, each SPNT switch network selects the output to any of the N inputs in any combination with up to all N inputs being selected on. Collectively, the individual 1xc3x97N networks formed by each combination of SPNT switch and its corresponding impedance converter/amplitude compensation network comprises the Nxc3x97M network.
In all switch conditions, the impedance and insertion loss of each SPNT switch is maintained by an impedance converter/amplitude compensation network. The number of output ports determines the number (M) of 1xc3x97N networks in the matrix. The number of input ports is set by the number of legs (N) in the SPNT switch. By placing the SPNT switch as the last element before the output, the number of cross over points is maintained at a number which can be readily calculated based on the number of inputs and outputs.